ST-Ericsson is a pioneer in packaging technologies, delivering highly integrated solutions that utilize die, package and PWB co-design for best-in-class performance, footprint and cost. We have a close collaboration with our parent company STMicroelectronics and partnership with top tier packaging houses and R&D centers to ensure optimized and future-proof solutions to our customers.
The Package on Package (PoP) technology is the most common package for our smartphone solutions. Placing the memories on the top package and the logic die in the bottom package, for smallest footprint and for best signal performance, will continue to be the dominating technology for the smartphone segment.
For thin modems, small integrated solutions are achieved using system in package (SiP). In a SiP solution, multiple dies are placed in the same package using the same or different interconnection technologies.
BGA is one of the reference packaging solutions in the industry today and used in a majority of ST-Ericsson’s platforms. We are proposing BGA packages with either interconnection made of wire bond, flip chip, or a combination of both. Our BGA offer includes Package on Package (PoP), System in Package (SiP) and modules.
The trend towards higher-end smartphones and the need for higher bandwidth in between multimedia processing units and memories is calling for a disruptive approach in terms of interconnect density. ST-Ericsson is utilizing Through Silicon Via (TSV) to create vertical short access paths and connect chips. TSV is a new and promising interconnect technology enabler which is maturing fast. It consists in etching vertical small holes of a few microns in wafers and filled with metal, making it possible for connections between dies stacked on top of each other.
Wafer Level Chip Scale Package (WLCSP) is a growing type of packaging in cell phones. Enabling great miniaturization and performance results, WLCSP can be divided into two categories, both used by ST-Ericsson on its latest products: Fan-In Wafer Level Packaging (FI WLP) and Fan-Out Wafer Level Packaging (FO WLP). In both cases, no laminate substrate is needed to connect the die to the PWB. BGA balls are directly attached onto the silicon die and/or the fan out area. FI WLP fits devices with small dies and relatively low I/O count. FO WLP could manage larger packages and higher I/O count. With FI WLP and FO WLP (also called eWLB) a solder ball pitch can be maintained that is easily handled on the PWB.
The FO WLP technology has the potential to reduce package thickness, to be used for next generation PoP packages and passive integration, and opens a broad range of new packaging integration possibilities for future designs. ST-Ericsson is actively investigating these potential opportunities to deliver leading edge solutions to its customers.
Traditional planar CMOS on bulk silicon technology is facing great challenges when approaching 28nm, and things will only get worse. A solution is fully depleted silicon-on-insulator, or FD-SOI, which combines a low-disruption planar approach while offering a very worthwhile operating frequency boost and very low standby and active power at chip level, making this technology particularly well suited for mobile application processor.
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